PLL Category Block Listing

The following blocks are included in the PLL category :

• Charge Pump
• Loop Filter (2nd Order PLL)
• Loop Filter (3rd Order PLL)
• Type 2 Phase Detector
• Type 3 Phase Detector
• Type 4 Phase Detector

Charge Pump

This block implements a first order active lag-lead loop filter for use in a second order digital PLL. The UP and DOWN inputs are assumed to be binary and represent the output error signals from a type-3 or type-4 digital phase/frequency detector. The output is used to drive a VCO block.

The approximate PLL noise loop bandwidth, as well as the computed transfer function coefficients (tau1, tau2), are displayed in the dialog box based on the values of the other parameters. In order for the PLL to operate properly, the simulation sampling frequency must be much larger than the PLL natural frequency.

Loop Filter (2nd Order PLL)

This block implements a first order lag-lead loop filter for use in a second order analog PLL. A choice of active or passive loop design is provided. The input is assumed to be an error signal from a phase detector. The output is typically used to drive a VCO block. Both input and output are expressed in volts.

The Loop Filter (2nd Order PLL) block is able to track a phase or frequency step, but not doppler rate; for this, please use the Loop Filter (3rd Order PLL) block.

The PLL noise loop bandwidth, as well as the computed transfer function coefficients (tau1, tau2), are displayed in the dialog box based on the values of the other parameters. In order for the PLL to operate properly, the simulation sampling frequency must be much larger than the PLL natural frequency.

Loop Filter (3rd Order PLL)

This block implements a Wiener optimal second order loop filter for use in a third order analog PLL. A third order PLL is able to track a frequency ramp (Doppler rate), as well as a phase or frequency step.

The input is assumed to be an error signal from a phase detector. The output is typically used to drive a VCO block. Both input and output are expressed in volts.

The PLL Noise Loop Bandwidth is displayed in the dialog box based on the values of the other parameters. In order for the PLL to operate properly, the simulation sampling frequency must be much larger than the PLL natural frequency.

Type 2 Phase Detector

This block implements an XOR based digital phase detector. Block parameters include the input threshold voltage level, which is used to internally convert the input signals to digital waveforms [0, 1]. This block is usually followed by a Loop Filter block if used within a PLL.

Type 3 Phase Detector

This block implements an edge triggered digital phase/frequency detector based on the JK flip-flop. Unlike a type-2 detector, the type-3 implementation is sensitive to frequency and is independent of the duty cycle ratio of the input signals.

Block parameters include the initial output state, clock edge mode, and the low and high threshold voltage levels. This block is usually followed by a Charge Pump block.

Type 4 Phase Detector

This block implements an edge triggered digital phase/frequency detector. Compared to a type-3 detector, the type-4 implementation exhibits improved sensitivity to frequency offsets and has, at least theoretically, an infinite pull-in range.

Block parameters include the low and high threshold voltage levels. This block is usually followed by a Charge Pump block.