Digital Category Block Listing

The following blocks are included in the Digital category :

• Accumulate and Dump
• Binary Counter
• Bits to Symbol
• Buffer
• D Flip Flop
• Divide by N
• JK Flip Flop
• Mux/Demux
• Packet Timing
• Parallel to Serial
• Pulse Extend
• Queue
• Serial to Parallel
• State Machine
• Symbol to Bits
• Unbuffer

Accumulate and Dump

This block provides a clocked Accumulate and Dump function. At each input clock pulse, the block adds the current input value to its internal accumulator register. The accumulator is then “dumped” (output) when a clock pulse occurs at the dump input. Once dumped, the accumulator is reset to zero.

This block can be configured to either dump first and then accumulate, or viceversa. The output can also be optionally averaged by dividing by the number of input values read.

Binary Counter

This block implements a binary counter with optional edge trigger. The internal counter will increment each time a rising (or falling) edge is detected, or wheneve the input is above a set threshold. Once the counter has reached an internal “all ones” state, the next event resets the counter to zero and produces an output pulse on the Carry flag output. Block parameters include the number of bits for the counter, clock edge mode, the counter initial value, and edge threshold voltage.

Bits to Symbol

This block combines n parallel binary bit streams into a single symbol value. The mapping is simply the decimal equivalent of the binary number formed by combining the input bit streams. Rounding is performed on the input data. Any value > 0.5 is considered a 1, otherwise it is considered a 0. The number of binary inputs is a user defined variable.

Buffer

This block is used to pack elements of a serial data stream into a vector "frame". Reading of the input data is controlled via an external clock. Data can be written to the output vector in either ascending or descending order.

This block is implemented using a circular buffer rather than a sliding buffer. Once the end of the buffer is reached, writing starts again at the beginning of the buffer, overwriting previous data. The buffer is initialized to all zeros at the start of a simulation.

D Flip Flop

This block implements an edge-triggered D type flip flop. Block parameters include the initial flip flop state, clock edge mode, and edge threshold voltage. The clock input for this block, unlike most Comm blocks, is not a pulse train but rather a rectangular type waveform.

Divide by N

This block implements a digital divide by N function. An internal counter is used to produce an output clock transition for every N detected input clock transitions. Block parameters include the divide ratio, initial delay, and clock threshold voltage.

The Divide by N block works on the rising and falling edges of the input waveform, and can accept either an impulse train or a rectangular pulse train as its input.

JK Flip Flop

This block implements an edge-triggered JK type flip flop. Block parameters include the initial flip flop state, clock edge mode, and edge threshold voltage. The clock input for this block, unlike most Comm blocks, is not a pulse train but rather a rectangular type waveform.

Mux/Demux

This block implements a digital multiplexer or demultiplexer. A multiplexer combines several low speed data streams into a single high speed stream. A demultiplexer reverses the operation.

The Mux/Demux block can be controlled by an internal or external clock. At each clock pulse, the current active input (output) of the multiplexer (demultiplexer) is advanced by 1 in round robin fashion.

Packet Timing

This block produces packet-timing signals for use in generating fixed length or variable length packet structures. Up to eight different sections can be strung together using this block, each with its own length specified as a multiple of an underlying clock interval. For example, a packet may have three sections comprised of the packet header, payload data, and a CRC, each with different lengths. Clock timing can be either generated internally or provided externally.

As the block cycles through the specified number of sections (N ), it provides control signals (ON/OFF) to individual outputs corresponding to each section. Only one of these outputs will be ON at any given time. In addition, a “state” output is provided to indicate the active section of the packet. Note: The State output is zero indexed and ranges over [ 0, N-1]. Once the last section has been completed, the block restarts at the beginning.

In a typical configuration, the block’s control lines can be used to enable the clocking (ON/OFF) of individual signal sources corresponding to each section of the packet (e.g. header, payload, CRC), and the state output can be used to control which signal is passed to the next stage in the simulation diagram using a case block (Blocks/Nonlinear).

Parallel to Serial

This block accepts parallel data represented by symbol numbers and outputs a serial binary stream. The output bits are obtained by decomposing the binary representation of the input symbol number.

The bits can be output either LSB first or MSB first. The user must specify the width of the parallel word in bits and the output bit rate.

Pulse Extend

This block is used to extend the duration of a clock impulse for a specified time interval, represented as either a number of simulation steps or time in seconds. This block preserves the amplitude of the original input pulse.

Queue

This block implements a digital queue. The queue service can be specified as either first-in first-out (FIFO) or last-in first-out (LIFO). This block can be used to simulate buffers used in communication systems. Input values are stored in the queue according to an input clock and are read out according to an output clock.

Besides the data output, the Queue block also provides the current number of values stored in the queue and an overflow indicator flag.

Serial to Parallel

This block accepts a serial binary stream and outputs parallel data as symbol numbers. The bits can be provided either LSB first or MSB first. The symbol value is obtained by combining sets of n input bits at a time, where n is a user specified parameter.

State Machine

This block implements a digital State Machine. Each time the clock input for the block is “high”, the block will transition to a new “state” depending on its current state and the value of the block’s input. The block can control up to 10 outputs.

An external State Transition Map File is used to control the block’s behavior. For each possible combination of “current state/input value”, this file specifies the next state and unique values for each of the block’s N outputs.

Symbol to Bits

This block accepts a symbol number and outputs n parallel binary bit streams. The mapping is obtained by decomposing the binary representation of the symbol number. You can specify the number of output data streams.

Unbuffer

This block accepts an input data vector of a specified size and outputs a serial data stream. The reading of the input vector is controlled via an external read strobe. The serial output can be controlled using either an internal or external clock.